Analog and mixed-signal testing is an important issue that affects both the time-to-market and product cost of many modem electronic systems. One key to the success of products with these properties is Built-In Self-Test (BIST) of circuits and systems. Although BIST for digital IC's is widely used [1], manufacturers of mixed-signal IC's are still searching for an appropriate BIST solution [3-8]. An important concern of IC manufacturers is the “overhead” required to implement BIST on their systems.
The phase-locked loop (PLL) is a mixed-signal block used in a large number of applications such as frequency synthesis, phase demodulation, clock distribution and timing recovery. It is thus essential for systems like wireless phones, optical fiber links and micro-computers. PLLs are even expected to appear soon on other purely digital circuits such as field-programmable gate arrays (FPGA) and digital signal processors (DSP). But the PLL is one of the most difficult system to apply a BIST scheme, due to its tight feedback [9].
Previous literatures in PLL BIST have focused on functional evaluation of the PLL under test. Testing using functional specifications verifies the functionality of the circuit at some pre-specified test points. On-chip measurement of the jitter transfer function technique emphasizes on-chip jitter generation and output jitter measurement [6], [13]. The technique described in [6], [13] suffers from area overhead, due to the fact that it needs a delta-sigma modulator to generate the jitter inside the chip. This technique also suffers from analog node loading problems. In [10] a method is presented to convert a closed loop circuit requiring frequency measurement into an open loop circuit in which dynamic delay is measured. Recent work re-configures the PLL in a new structure allowing a simple Boolean test to be applied [14]. These two techniques described in [10, 14] break the VCO oscillation loop which is the most sensitive analog path in the PLL. This has a significant alteration in the VCO linearity and range, as well as the overall PLL characteristics in high-frequency applications. A technique introduced in [12] reports to test the PLL by performing on-chip measurement of certain functional specifications and comparing them on-chip to ATE (Automated Test Equipment)-supplied digital limits using digital circuitry. ATE generally means external test systems. This technique has the disadvantages of requiring an ATE and also a PLL lock indicator inside the chip, which increases the overall test cost. For the signal injection method, the matching to the two charge-pumps is a cause of errors.
Functional testing can result in either excessive or insufficient testing of the circuit. Fault-based testing is an alternative to functional testing, which targets the presence of physical defects in a PLL, thus providing a quantitative measure of the test process [11].
Studies on a number of analog circuits show that relatively simple tests can give high test coverage for common defects, and this can be achieved by using the defect-oriented testing approach [16]. At the same time it also became clear that these tests are not able to cover all faulty products caused by process parametric variations. However, as the result of the ever increasing functional complexity of mixed-signal ICs and the improved IC fabrication-process control, spot defects are the dominant yield limiter in a mature process and a dominant cause of customer rejects for a product in high volume production [2].
Described here is a new BIST technique for clock and oscillator circuits based on defect-oriented testing, which uses existing analog components to reduce area overhead and for practical high-speed PLL applications. This scheme can incorporate IEEE 1149.1 boundary scan architecture for easy access of the BIST output, use the existing scan path if available, or use other scanning techniques known to the art. One advantage of this technique is that there is no change to the sensitive analog blocks. This ensures that the characteristics of the loop-filter, charge-pump, and VCO are not altered by using the described BIST scheme.